From 1be7784fbbfb17eb394ef6693aff56ea88aa3613 Mon Sep 17 00:00:00 2001 From: Mathieu Serandour Date: Sun, 5 Dec 2021 00:14:08 +0100 Subject: [PATCH] flags 32bit -> 64bit: support XD --- kernel/memory/paging.c | 4 ++-- kernel/memory/paging.h | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/kernel/memory/paging.c b/kernel/memory/paging.c index 35dd06e..cdb0faa 100644 --- a/kernel/memory/paging.c +++ b/kernel/memory/paging.c @@ -100,7 +100,7 @@ static uint32_t pml4_offset(uint64_t virt) { // PWT: page level write-through // PCD: page level cache disable -static void* create_table_entry(void* entry, unsigned flags) { +static void* create_table_entry(void* entry, uint64_t flags) { assert_aligned(entry, 0x1000); return (void*)(flags | @@ -434,7 +434,7 @@ static void* get_entry_or_allocate(void** restrict table, unsigned index) { void map_pages(uint64_t physical_addr, uint64_t virtual_addr, size_t count, - unsigned flags) { + uint64_t flags) { while(count > 0) { // fetch table indexes diff --git a/kernel/memory/paging.h b/kernel/memory/paging.h index f1c9e5e..0b4af2e 100644 --- a/kernel/memory/paging.h +++ b/kernel/memory/paging.h @@ -21,13 +21,13 @@ void append_paging_initialization(void); // the entry is present #define PRESENT_ENTRY 1llu // read only -#define PL_RW 2 +#define PL_RW 2llu // supervisor only -#define PL_US 4 +#define PL_US 4llu // page level write through -#define PWT 8 +#define PWT 8llu // page level cache disable -#define PCD 16 +#define PCD 16llu #define PL_XD (1llu << 63) /** @@ -44,8 +44,8 @@ void append_paging_initialization(void); void map_pages(uint64_t physical_addr, uint64_t virtual_addr, size_t count, - unsigned flags); + uint64_t flags); void alloc_pages(void* virtual_addr, size_t count, - unsigned flags); + uint64_t flags);