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109 lines
4.3 KiB
109 lines
4.3 KiB
#pragma once
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#include <stdint.h>
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struct cpuid_regs {
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uint32_t eax, ebx, ecx, edx;
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};
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void cpuid(uint32_t eax, struct cpuid_regs* out_regs);
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// doc from
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/**
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*
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Basic CPUID Information
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Initial EAX Value Register Information Provided about the Processor
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0H EAX Maximum Input Value for Basic CPUID Information (see second table)
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- EBX "Genu"
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- ECX "ntel"
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- EDX "ineI"
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01H EAX Version Information: Type, Family, Model, and Stepping ID
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- EBX Bits 7-0: Brand Index
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- - Bits 15-8: CLFLUSH line size (Value . 8 = cache line size in bytes)
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- - Bits 23-16: Number of logical processors per physical processor; two for the Pentium 4
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processor supporting Hyper-Threading Technology
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- - Bits 31-24: Local APIC ID
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- ECX Extended Feature Information (see fourth table)
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- EDX Feature Information (see fifth table)
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02H EAX Cache and TLB Information (see sixth table)
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- EBX Cache and TLB Information
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- ECX Cache and TLB Information
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- EDX Cache and TLB Information
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03H ECX Bits 00-31 of 96 bit processor serial number. (Available in Pentium III processor only;
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otherwise, the value in this register is reserved.)
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- EDX Bits 32-63 of 96 bit processor serial number. (Available in Pentium III processor only;
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otherwise, the value in this register is reserved.)
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- - NOTE: Processor serial number (PSN) is not supported in the Pentium 4 processor or later.
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On all models, use the PSN flag (returned using CPUID) to check for PSN support before
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accessing the feature. See AP-485, Intel Processor Identification and the CPUID Instruction
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(Order Number 241618) for more information on PSN.
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04H EAX Bits 4-0: Cache Type**
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- - Bits 7-5: Cache Level (starts at 1)
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- - Bits 8: Self Initializing cache level (does not need SW initialization)
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- - Bits 9: Fully Associative cache
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- - Bits 13-10: Reserved
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- - Bits 25-14: Number of threads sharing this cache*
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- - Bits 31-26: Number of processor cores on this die (Multicore)*
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- EBX Bits 11-00: L = System Coherency Line Size*
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- - Bits 21-12: P = Physical Line partitions*
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- - Bits 31-22: W = Ways of associativity*
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- ECX Bits 31-00: S = Number of Sets*
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- EDX Reserved = 0
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- - 0 = Null - No more caches
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- - 1 = Data Cache
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- - 2 = Instruction Cache
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- - 3 = Unified Cache
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- - 4-31 = Reserved
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- - NOTE: CPUID leaves > 3 < 80000000 are only visible when IA32_CR_MISC_ENABLES.BOOT_NT4 (bit
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22) is clear (Default)
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5H EAX Bits 15-00: Smallest monitor-line size in bytes (default is processor's monitor granularity)
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- EBX Bits 15-00: Largest monitor-line size in bytes (default is processor's monitor granularity)
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*Add one to the value in the register file to get the number. For example, the number of processor cores is EAX[31:26]+1.
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** Cache Types fields
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Extended Function CPUID Information
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Initial EAX Value Register Information Provided about the Processor
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80000000H EAX Maximum Input Value for Extended Function CPUID Information (see second table).
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- EBX Reserved
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- ECX Reserved
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- EDX Reserved
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80000001H EAX Extended Processor Signature and Extended Feature Bits. (Currently reserved)
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- EBX Reserved
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- ECX Reserved
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- EDX Reserved
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80000002H EAX Processor Brand String
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- EBX Processor Brand String Continued
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- ECX Processor Brand String Continued
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- EDX Processor Brand String Continued
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80000003H EAX Processor Brand String Continued
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- EBX Processor Brand String Continued
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- ECX Processor Brand String Continued
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- EDX Processor Brand String Continued
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80000004H EAX Processor Brand String Continued
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- EBX Processor Brand String Continued
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- ECX Processor Brand String Continued
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- EDX Processor Brand String Continued
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80000005H EAX Reserved = 0
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- EBX Reserved = 0
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- ECX Reserved = 0
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- EDX Reserved = 0
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80000006H EAX Reserved = 0
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- EBX Reserved = 0
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- ECX Bits 0-7: Cache Line Size
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- - Bits 15-12: L2 Associativity
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- - Bits 31-16: Cache size in 1K units
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- EDX Reserved = 0
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- 80000007H EAX Reserved = 0
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- EBX Reserved = 0
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- ECX Reserved = 0
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- EDX Reserved = 0
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80000008H EAX Reserved = 0
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- EBX Reserved = 0
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- ECX Reserved = 0
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- EDX Reserved = 0
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*/
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